EP20K600CB652C8N vs EP20K600CB652C7ES Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CB652C8N sa pamamagitan ng Altera at EP20K600CB652C7ES sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K600CB652C8N | EP20K600CB652C7ES |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Device Type | Loadable PLD / FPGA | — |
| System Gates | 600,000 | 600,000 |
| Logic Elements | 24,320 cells | 24,320 |
| Embedded Memory | 311,296 bits | — |
| User I/O Pins | 488 | — |
| Dedicated Inputs | 4 | — |
| Outputs | 480 | — |
| Propagation Delay (typ.) | 1.48 ns | — |
| Pin-to-Pin Timing | 1.78 ns | — |
| Internal Frequency (typ.) | 301.21 MHz | — |
| Core Supply Voltage | 1.8 V nominal (1.71 V to 1.89 V) | — |
| Process Technology | 0.18 µm all-layer copper-metal | 0.15 µm CMOS |
| Speed Grade | C8 | — |
| Temperature na Operasyon | 0 °C to 85 °C (commercial) | 0 °C to +85 °C (commercial) |
| Packhaging | 652-ball LBGA, 45 x 45 mm, 1.27 mm pitch | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Architecture | MultiCore LUT + Embedded System Blocks (ESB) | — |
| Pin-Compatible With | APEX 20KE family | — |
| Tindminan RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Maximum System Gates | — | 1,053,840 |
| Embedded Memory Bits | — | 311,296 |
| Embedded System Blocks (ESB) | — | 26 |
| Maximum User I/O | — | 488 |
| User I/O (this package) | — | 488 (652-BGA) |
| Supply Voltage - Core | — | 1.71 V to 1.89 V (1.8 V nominal) |
| Maximum Internal Clock Frequency | — | 1666.6 MHz |
| Propagation Delay | — | 1.6 ns |
| Package Type | — | 652-ball FineLine BGA |
| JEDEC Package Code | — | S-PBGA-B652 |
| Configuration Modes | — | Passive Serial, Passive Parallel, JTAG |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| PLLs | — | 4 |