EP20K600CB652C9N vs EP20K600CB652C8N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CB652C9N sa pamamagitan ng Intel at EP20K600CB652C8N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K600CB652C9N EP20K600CB652C8N
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family APEX 20KC APEX 20KC
Device Type Loadable PLD (FPGA) Loadable PLD / FPGA
Typical Gates 600,000 —
Logic Elements 24,320 24,320 cells
Maximum User I/O 488 —
Packhaging BGA-652 (652-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch) 652-ball LBGA, 45 x 45 mm, 1.27 mm pitch
Process Technology 0.15 micron all-layer copper CMOS 0.18 µm all-layer copper-metal
Core Supply Voltage 1.8 V 1.8 V nominal (1.71 V to 1.89 V)
Speed Grade C9 (~1.48 ns propagation delay) C8
Architecture MultiCore LUT + embedded system memory (ESB) MultiCore LUT + Embedded System Blocks (ESB)
On-chip Memory Embedded system memory blocks (dual-port RAM, FIFO) —
Configuration Interface JTAG (IEEE 1149.1) and serial/PROM configuration —
Temperature na Operasyon 0 C to 85 C (commercial) 0 °C to 85 °C (commercial)
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount (BGA)
Pin/Pin Compatibility Pin-compatible with APEX 20KE devices of same package —
Toolchain Altera/Intel Quartus II (legacy APEX support) —
Tindminan RoHS [DATA_NEEDED: rohs status] unknown
Level ng MSL [DATA_NEEDED: MSL level] —
System Gates — 600,000
Embedded Memory — 311,296 bits
User I/O Pins — 488
Dedicated Inputs — 4
Outputs — 480
Propagation Delay (typ.) — 1.48 ns
Pin-to-Pin Timing — 1.78 ns
Internal Frequency (typ.) — 301.21 MHz
Pin-Compatible With — APEX 20KE family

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