EP20K600CB652C9N vs EP20K600CB652I9N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CB652C9N sa pamamagitan ng Intel at EP20K600CB652I9N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K600CB652C9N EP20K600CB652I9N
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family APEX 20KC APEX 20KC
Device Type Loadable PLD (FPGA) —
Typical Gates 600,000 —
Logic Elements 24,320 24,320
Maximum User I/O 488 —
Packhaging BGA-652 (652-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch) 652-BGA (PBGA652)
Process Technology 0.15 micron all-layer copper CMOS 0.15 um CMOS
Core Supply Voltage 1.8 V —
Speed Grade C9 (~1.48 ns propagation delay) —
Architecture MultiCore LUT + embedded system memory (ESB) —
On-chip Memory Embedded system memory blocks (dual-port RAM, FIFO) —
Configuration Interface JTAG (IEEE 1149.1) and serial/PROM configuration —
Temperature na Operasyon 0 C to 85 C (commercial) -40C to +100C (Industrial)
Uri ng Pagpapasok Surface Mount (BGA) —
Pin/Pin Compatibility Pin-compatible with APEX 20KE devices of same package —
Toolchain Altera/Intel Quartus II (legacy APEX support) —
Tindminan RoHS [DATA_NEEDED: rohs status] —
Level ng MSL [DATA_NEEDED: MSL level] —
System Gates — 600,000
Maximum Operating Frequency — 250 MHz
Core Voltage — 1.8 V
I/O Voltage — 3.3 V
Total I/O Pins — 488
General-Purpose I/O — 480
Dedicated Inputs — 4
Terminal Pitch — 1.27 mm
Configuration Method — Passive Serial / Passive Parallel / JTAG
Embedded Memory — ESB (Embedded System Block) RAM / CAM
I/O Standards — LVDS, PCI, LVTTL, LVCMOS

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