EP20K600CF1020C9 vs EP20K600CF33C9 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CF1020C9 sa pamamagitan ng Intel at EP20K600CF33C9 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP20K600CF1020C9 - APEX 20KC FPGA 600K Gates 250MHz 1020-FBGA | Intel
EP20K600CF1020C9 ObsoletePagsanggunian na paghahambing
| Parametro | EP20K600CF1020C9 | EP20K600CF33C9 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements | 24,320 | — |
| System Gates | 600,000 | 600,000 (maximum) |
| Maximum Operating Frequency | 250 MHz | 250 MHz |
| Embedded Memory (ESB) | Configurable dual-port RAM / FIFO / CAM / ROM | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm CMOS |
| Internal Supply Voltage (VCCINT) | 1.8 V | — |
| I/O Supply Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| User I/O Pins | 588 | — |
| Dedicated Inputs | 4 | — |
| Total I/O Count (in/out) | 580 / 580 | — |
| Packhaging | 1020-ball FC-FBGA (33 x 33 mm, 1.00 mm pitch) | 1020-ball FC-FBGA |
| JESD-30 Package Code | S-PBGA-B1020 | — |
| Temperature na Operasyon | 0°C to 85°C (TJ) | — |
| PCI Compliance | PCI Local Bus Spec Rev 2.2 (33/66 MHz, 32/64-bit, 3.3 V) | — |
| External Memory Support | DDR SDRAM, ZBT SRAM | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs status] |
| Logic Elements / Cells | — | 24,320 |
| Maksimum na Taktiko ng Oras | — | 303.03 MHz |
| Propagation Delay | — | 2.0 ns |
| Core Supply Voltage (VCCINT) | — | 1.8 V nominal (1.71 V to 1.89 V) |
| User I/O | — | 588 (4 dedicated inputs + 580 general-purpose I/O) |
| Uri ng Pagpapasok | — | Surface Mount (BGA) |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |
| Embedded RAM | — | Dual-port RAM blocks (per family) |
| Programmability | — | JTAG / IEEE 1149.1 ISP, SRAM-based |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Logic Block Architecture | — | MultiCore (LUT + product-term + embedded memory) |
| I/O Standards Supported | — | LVTTL, LVCMOS, LVDS (per family datasheet) |