EP20K600CF672C-9 vs EP20K600CF672C-8 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CF672C-9 sa pamamagitan ng Altera at EP20K600CF672C-8 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K600CF672C-9 EP20K600CF672C-8
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Type FPGA (APEX 20KC family, complex PLD) FPGA (Field Programmable Gate Array)
Typical Gate Count 600,000 gates —
Logic Elements (LEs) [DATA_NEEDED: logic element count] 24,320
Embedded System Blocks (ESBs) [DATA_NEEDED: ESB count and total RAM bits] —
User I/Os 488 pins —
PLLs 4 —
Packhaging 672-ball FBGA (45 x 45 mm, 1.27 mm pitch) —
Bilang ng Pin 672 —
Core Supply Voltage (VCCINT) 1.8 V —
I/O Supply Voltage (VCCIO) 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) —
Propagation Delay 1.48 ns —
Temperature na Operasyon 0 °C to +85 °C (commercial) —
Speed Grade -9 -8
Process Technology 0.15 µm all-layer copper interconnect 0.15 micrometer all-layer copper-metal
Configuration Interface Serial (EPC16 / EPC8 / EPC4 / EPC2 / EPC1) —
Uri ng Pagpapasok Surface Mount (BGA) —
Tindminan RoHS unknown [DATA_NEEDED: RoHS status]
Series — APEX 20KC
Typical Gates — 600,000
Embedded Memory Bits — 311,296
Maximum User I/Os — 508
Bilang ng Pins — 672
Package Type — 672-BGA (FineLine BGA, 1.27 mm pitch, 45 x 45 mm)
Propagation Delay (tPD) — 1.48 ns
Architecture — MultiCore (LUT logic + embedded memory)
Hanay ng Temperature na Operasyon — 0C to +85C (commercial)
Volte ng Pagbibigay — Multi-rail (core + I/O banks)
Configuration Method — Serial / parallel / JTAG
Pin Compatibility — Pin-compatible with APEX 20KE family

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