EP20K600CF672C6 vs EP20K600CF672C-9 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CF672C6 sa pamamagitan ng Altera at EP20K600CF672C-9 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K600CF672C6 EP20K600CF672C-9
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family APEX 20KC —
Typical Gate Count 600,000 gates 600,000 gates
Logic Elements (LEs) 24,320 [DATA_NEEDED: logic element count]
Embedded System Blocks (ESBs) 160 (each 2,048 bits) [DATA_NEEDED: ESB count and total RAM bits]
Maximum Embedded RAM 311,296 bits (311 kbit) —
Maximum User I/O Pins 508 —
Packhaging 672-ball FineLine BGA (CF672) 672-ball FBGA (45 x 45 mm, 1.27 mm pitch)
Package Body Size 27 mm × 27 mm —
Speed Grade -6 (C6) -9
Temperature na Operasyon 0 °C to +85 °C (commercial) 0 °C to +85 °C (commercial)
Core Voltage 1.8 V —
I/O Standards Supported LVCMOS, LVTTL, HSTL, SSTL, GTL+ —
Embedded PLLs 4 —
Process Technology 0.18 µm CMOS, 6 metal layers 0.15 µm all-layer copper interconnect
Configuration Method SRAM-based, JTAG, EPC16/EPC2 —
Tindminan RoHS Non-RoHS (legacy process) unknown
Device Type — FPGA (APEX 20KC family, complex PLD)
User I/Os — 488 pins
PLLs — 4
Bilang ng Pin — 672
Core Supply Voltage (VCCINT) — 1.8 V
I/O Supply Voltage (VCCIO) — 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O)
Propagation Delay — 1.48 ns
Configuration Interface — Serial (EPC16 / EPC8 / EPC4 / EPC2 / EPC1)
Uri ng Pagpapasok — Surface Mount (BGA)

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