EP20K600CF672C6 vs EP20K600CF672C-9 比較
詳細並排比較 EP20K600CF672C6 由 Altera 與 EP20K600CF672C-9 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP20K600CF672C-9 - 600K Gates APEX 20KC FPGA 488 I/O BGA-672 | Altera
EP20K600CF672C-9 Obsolete規格比較
| 參數 | EP20K600CF672C6 | EP20K600CF672C-9 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20KC | — |
| Typical Gate Count | 600,000 gates | 600,000 gates |
| Logic Elements (LEs) | 24,320 | [DATA_NEEDED: logic element count] |
| Embedded System Blocks (ESBs) | 160 (each 2,048 bits) | [DATA_NEEDED: ESB count and total RAM bits] |
| Maximum Embedded RAM | 311,296 bits (311 kbit) | — |
| Maximum User I/O Pins | 508 | — |
| 封裝 | 672-ball FineLine BGA (CF672) | 672-ball FBGA (45 x 45 mm, 1.27 mm pitch) |
| Package Body Size | 27 mm × 27 mm | — |
| Speed Grade | -6 (C6) | -9 |
| 工作溫度 | 0 °C to +85 °C (commercial) | 0 °C to +85 °C (commercial) |
| Core Voltage | 1.8 V | — |
| I/O Standards Supported | LVCMOS, LVTTL, HSTL, SSTL, GTL+ | — |
| Embedded PLLs | 4 | — |
| Process Technology | 0.18 µm CMOS, 6 metal layers | 0.15 µm all-layer copper interconnect |
| Configuration Method | SRAM-based, JTAG, EPC16/EPC2 | — |
| RoHS 狀態 | Non-RoHS (legacy process) | unknown |
| Device Type | — | FPGA (APEX 20KC family, complex PLD) |
| User I/Os | — | 488 pins |
| PLLs | — | 4 |
| 腳位數 | — | 672 |
| Core Supply Voltage (VCCINT) | — | 1.8 V |
| I/O Supply Voltage (VCCIO) | — | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) |
| Propagation Delay | — | 1.48 ns |
| Configuration Interface | — | Serial (EPC16 / EPC8 / EPC4 / EPC2 / EPC1) |
| 安裝類型 | — | Surface Mount (BGA) |