EP20K600CF672C7ES vs EP20K600CF672C9 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CF672C7ES sa pamamagitan ng Altera at EP20K600CF672C9 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K600CF672C7ES - APEX 20KC FPGA 600K Gates 672-FBGA | Altera
EP20K600CF672C7ES ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP20K600CF672C7ES | EP20K600CF672C9 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Series | APEX 20KC | — |
| Family | APEX 20K | — |
| Logic Elements / Cells | 24320 | — |
| System Gates | 600000 | — |
| Maximum User I/O | 504 | 488 pins |
| Maximum Input Lines | 508 | — |
| Number of Macrocells | 504 | — |
| Maximum Operating Frequency | 375.94 MHz (per FPGAkey listing) | — |
| Propagation Delay | 1.6 ns | 1.48 ns |
| Internal Reference Clock | 1666.6 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm all-layer copper-metal |
| Core Supply Voltage (VCCINT) | 1.8 V | — |
| Package Type | FC-FBGA | 672-pin FC-FBGA |
| Pin / Ball Count | 672 | — |
| Grade Suffix | ES (engineering sample / extended screening) | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature grade] | 0 °C to +85 °C (commercial) |
| Uri ng Pagpapasok | Surface Mount (BGA) | — |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Configuration Memory | SRAM-based (volatile) | — |
| Device Family | — | APEX 20KC |
| Typical Gate Count | — | 600,000 gates |
| Logic Elements (LEs) | — | 24,320 |
| Embedded Memory (EAB) | — | 311 Kbits |
| Maximum Internal Frequency | — | 250 MHz |
| Core Voltage | — | 1.8 V |
| Package Dimensions | — | 45 x 45 mm, 1.27 mm pitch |
| Total Pin Count | — | 652 balls |
| Configuration Interface | — | IEEE 1149.1 JTAG / passive serial / EPC configuration |