EP20K600CF672C7N vs EP20K600CF672C-7ES Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CF672C7N sa pamamagitan ng Altera at EP20K600CF672C-7ES sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K600CF672C7N EP20K600CF672C-7ES
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Family APEX 20KC —
Maximum System Gates 1,052,000 1,560,000 (typical 600K application gates)
Typical Gates 600,000 —
Logic Elements / Cells 24,320 —
Maximum User I/O Pins 488 —
Total Package Pins 652 —
Packhaging FC-FBGA (BGA-652) 45 x 45 mm, 1.27 mm pitch 672-ball FCBGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch
Core Voltage 1.8 V 1.8 V (typical APEX 20KC, exact value per datasheet)
Maximum Operating Frequency 375.94 MHz —
Propagation Delay 1.48 ns 1.48 ns to 1.6 ns
Process Technology 0.15 µm all-layer copper-metal CMOS 0.15 micron all-layer copper CMOS
Architecture MultiCore (LUT + Embedded System Memory) —
Temperature na Operasyon 0 °C to +85 °C (Commercial) 0 C to 85 C (Commercial)
Speed Grade C7 -7
Seated Height 3.50 mm —
Uri ng Pagpapasok Surface Mount (BGA) —
Tindminan RoHS unknown —
Family — APEX 20KC
Device Type — Field Programmable Gate Array (FPGA)
Typical Logic Elements — 24,320 (per APEX 20KC 600K family)
Maximum User I/O — 488
Total I/O Lines — 504 (per Microchip USA listing)
Total Inputs — 508
Embedded System Blocks (ESBs) — 248
Embedded RAM — 248 Kbits (dual-port)
PLLs — 4
Maksimum na Taktiko ng Oras — 1666.6 MHz
Configuration Mode — EPC serial / JTAG IEEE 1149.1
Compliance — RoHS status unknown (verify with manufacturer datasheet)

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