EP20K600CF672C7N vs EP20K600CF672C-7ES 比較

詳細並排比較 EP20K600CF672C7N 由 Altera 與 EP20K600CF672C-7ES 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K600CF672C7N EP20K600CF672C-7ES
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Device Family APEX 20KC —
Maximum System Gates 1,052,000 1,560,000 (typical 600K application gates)
Typical Gates 600,000 —
Logic Elements / Cells 24,320 —
Maximum User I/O Pins 488 —
Total Package Pins 652 —
封裝 FC-FBGA (BGA-652) 45 x 45 mm, 1.27 mm pitch 672-ball FCBGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch
Core Voltage 1.8 V 1.8 V (typical APEX 20KC, exact value per datasheet)
Maximum Operating Frequency 375.94 MHz —
Propagation Delay 1.48 ns 1.48 ns to 1.6 ns
Process Technology 0.15 µm all-layer copper-metal CMOS 0.15 micron all-layer copper CMOS
Architecture MultiCore (LUT + Embedded System Memory) —
工作溫度 0 °C to +85 °C (Commercial) 0 C to 85 C (Commercial)
Speed Grade C7 -7
Seated Height 3.50 mm —
安裝類型 Surface Mount (BGA) —
RoHS 狀態 unknown —
Family — APEX 20KC
Device Type — Field Programmable Gate Array (FPGA)
Typical Logic Elements — 24,320 (per APEX 20KC 600K family)
Maximum User I/O — 488
Total I/O Lines — 504 (per Microchip USA listing)
Total Inputs — 508
Embedded System Blocks (ESBs) — 248
Embedded RAM — 248 Kbits (dual-port)
PLLs — 4
最大時脈頻率 — 1666.6 MHz
Configuration Mode — EPC serial / JTAG IEEE 1149.1
Compliance — RoHS status unknown (verify with manufacturer datasheet)

資料表與資源

瀏覽所有產品 建立 BOM 索取報價