EP20K600CF672I7N vs EP20K600CF672I-8ES Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CF672I7N sa pamamagitan ng Intel at EP20K600CF672I-8ES sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K600CF672I-8ES - APEX 20KC 600K-Gate FPGA, 672-BGA | Intel / Altera
EP20K600CF672I-8ES ObsoletePagsanggunian na paghahambing
| Parametro | EP20K600CF672I7N | EP20K600CF672I-8ES |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Technology | 0.15 µm CMOS | — |
| Maximum System Gates | 600,000 | — |
| Logic Elements | 24,320 | 24,320 |
| Maximum User I/O Pins | 508 | 508 |
| Maximum Internal Frequency | 376 MHz | — |
| Embedded System Blocks (ESBs) | 160 | — |
| Total Embedded RAM (max) | 311,296 bits | — |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 2.5 V / 3.3 V (MultiVolt, bank-dependent) | — |
| Packhaging | 672-ball FineLine BGA (FC-FBGA) | 672-ball BGA (FineLine BGA, 1.27 mm pitch) |
| Ball Pitch | 1.0 mm | — |
| Package Body Size | 27 mm × 27 mm | — |
| Speed Grade | I7 (-40 °C to +100 °C industrial) | -8 (slower) |
| Propagation Delay (typical) | 1.6 ns | — |
| Configuration Method | JTAG (IEEE 1149.1) + EPC configuration device | — |
| Lead-Free Finish (N suffix) | Yes | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | Non-compliant (legacy Altera leaded BGA process) |
| Typical Gates | — | 600,000 (ASIC-equivalent) |
| Embedded Memory Bits | — | 311,296 |
| Embedded PLLs | — | 4 |
| Core Voltage | — | 1.8 V |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, SSTL, HSTL, GTL+ |
| Process Technology | — | 0.18 micron CMOS SRAM |
| Temperature na Operasyon | — | -40C to +100C (Industrial) |
| Configuration Modes | — | Passive Serial, Fast Passive Parallel, Passive Parallel Asynchronous, JTAG |
| In-System Programmability | — | Yes (ISP via EPC16, EPC8, EPC4, EPC2, EPC1) |
| Level ng MSL | — | [DATA_NEEDED: moisture sensitivity level] |