EP20K600CF672I7N vs EP20K600CF672I-8ES 比較
詳細並排比較 EP20K600CF672I7N 由 Intel 與 EP20K600CF672I-8ES 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP20K600CF672I-8ES - APEX 20KC 600K-Gate FPGA, 672-BGA | Intel / Altera
EP20K600CF672I-8ES Obsolete規格比較
| 參數 | EP20K600CF672I7N | EP20K600CF672I-8ES |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Technology | 0.15 µm CMOS | — |
| Maximum System Gates | 600,000 | — |
| Logic Elements | 24,320 | 24,320 |
| Maximum User I/O Pins | 508 | 508 |
| Maximum Internal Frequency | 376 MHz | — |
| Embedded System Blocks (ESBs) | 160 | — |
| Total Embedded RAM (max) | 311,296 bits | — |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 2.5 V / 3.3 V (MultiVolt, bank-dependent) | — |
| 封裝 | 672-ball FineLine BGA (FC-FBGA) | 672-ball BGA (FineLine BGA, 1.27 mm pitch) |
| Ball Pitch | 1.0 mm | — |
| Package Body Size | 27 mm × 27 mm | — |
| Speed Grade | I7 (-40 °C to +100 °C industrial) | -8 (slower) |
| Propagation Delay (typical) | 1.6 ns | — |
| Configuration Method | JTAG (IEEE 1149.1) + EPC configuration device | — |
| Lead-Free Finish (N suffix) | Yes | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | Non-compliant (legacy Altera leaded BGA process) |
| Typical Gates | — | 600,000 (ASIC-equivalent) |
| Embedded Memory Bits | — | 311,296 |
| Embedded PLLs | — | 4 |
| Core Voltage | — | 1.8 V |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, SSTL, HSTL, GTL+ |
| Process Technology | — | 0.18 micron CMOS SRAM |
| 工作溫度 | — | -40C to +100C (Industrial) |
| Configuration Modes | — | Passive Serial, Fast Passive Parallel, Passive Parallel Asynchronous, JTAG |
| In-System Programmability | — | Yes (ISP via EPC16, EPC8, EPC4, EPC2, EPC1) |
| MSL 等級 | — | [DATA_NEEDED: moisture sensitivity level] |