EP20K600CF672I8 vs EP20K600CF672I9 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CF672I8 sa pamamagitan ng Altera at EP20K600CF672I9 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K600CF672I8 EP20K600CF672I9
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family APEX 20KC APEX 20KC
Device Type SPLD / FPGA —
Logic Elements / Cells 24,320 24,320
Macros (Logic Cells) 2432 —
Typical Gate Count 600,000 gates —
Embedded Memory 311,296 bits [DATA_NEEDED: total RAM bits]
User I/Os 488 to 508 —
Bilang ng Pins 652 (functional) / 672 (BGA balls) —
Propagation Delay (typical) 1.48 ns —
Internal Frequency (max) [DATA_NEEDED: max internal frequency in MHz] —
Core Supply Voltage 1.8 V —
Process Technology 0.15 µm all-layer copper 0.15 µm CMOS
Temperature na Operasyon 0 °C to +85 °C (Industrial) —
Package Type 672-ball BGA, 45 x 45 mm, 1.27 mm pitch —
Uri ng Pagpapasok Surface Mount Surface Mount (BGA)
Tindminan RoHS Compliant per legacy product records [DATA_NEEDED: RoHS status]
Configuration Interface JTAG / Passive Serial —
Design Tool Quartus II (legacy MAX+PLUS II) —
System Gates — 600,000
Maximum Operating Frequency — 250 MHz
Core Voltage — 1.8 V
Packhaging — 672-pin FC-FBGA
Temperature Grade — Industrial (-40°C to +85°C)
Speed Grade — 9 (fastest bin)
User I/O Pins — 311 (max)
Embedded Array Blocks (EABs) — [DATA_NEEDED: EAB count]
PLLs — Up to 4
I/O Standards Supported — LVTTL, LVCMOS, PCI, LVDS
Configuration Mode — Passive Serial / JTAG
Maximum Seated Height — 2.1 mm
Level ng MSL — [DATA_NEEDED: MSL level]
Lead-Free — [DATA_NEEDED: lead-free]

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