EP20K60EFC324-3N vs EP20K60EFC324-2N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K60EFC324-3N sa pamamagitan ng Altera at EP20K60EFC324-2N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K60EFC324-3N | EP20K60EFC324-2N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | APEX-20KE | APEX-20KE |
| Number of Logic Elements | 2560 Cells | — |
| Total Gates | 60K Gates (60000 typical) | — |
| Number of User I/Os | 196 | — |
| Packhaging / Kaso | 324-BGA / 324-FBGA (19x19) | 324-BGA (FineLine BGA, 19x19 mm) |
| Supplier Device Package | 324-FBGA (19x19) | 324-FBGA (19x19) |
| Core Supply Voltage | 1.71V ~ 1.89V (1.8V nominal) | — |
| Temperature na Operasyon | 0°C ~ 85°C (TJ) | — |
| Maximum Internal Frequency | 182 MHz (-3 speed grade) | — |
| Process Technology | 0.22 um CMOS | 0.22 µm CMOS |
| Bilang ng Pins | 324 | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Total RAM Bits | [DATA_NEEDED: total RAM bits per APEX 20K datasheet] | 32,768 |
| Embedded System Blocks | [DATA_NEEDED: ESB count] | — |
| I/O Standards Supported | [DATA_NEEDED: I/O standards list] | — |
| Tindminan RoHS | [DATA_NEEDED: explicit RoHS statement] | unknown |
| Packaging | Bulk (per distributor listing) | — |
| Ordering Suffix | -N suffix ordering variant | — |
| Family | — | APEX 20K |
| Number of Logic Elements/Cells | — | 2,560 |
| Total System Gates | — | 60,000 |
| Number of Logic Array Blocks (LABs/CLBs) | — | 2,560 |
| Number of I/O | — | 196 |
| Core Voltage Supply | — | 1.71 V to 1.89 V (1.8 V typ.) |
| Internal Frequency (max) | — | 200 MHz |
| Propagation Delay | — | 1.72 ns |
| Operating Temperature Range (TJ) | — | 0 °C to 85 °C (commercial) |
| Architecture | — | MultiCore (LUT + ESB memory + product-term) |
| Configuration Method | — | Passive Serial / JTAG (IEEE 1149.1) |