EP2A25F672C7N vs EP2A25F672C7 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP2A25F672C7N sa pamamagitan ng Altera at EP2A25F672C7 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP2A25F672C7N EP2A25F672C7
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family APEX II —
Logic Elements 24,320 cells 25,000
System Gates Approximately 900,000 —
User I/Os 492 —
Propagation Delay (tPD) 1.69 ns —
Internal Operating Frequency Up to 500 MHz —
Core Voltage (VCCINT) 1.5 V —
Process Technology 0.15 µm all-layer copper (up to 8 metal layers) 0.15-um all-layer copper, up to 8 metal layers
Logic Family CMOS —
Package Type 672-ball FC-FBGA (FineLine BGA) —
Package Body Size 27 x 27 mm —
Ball Pitch 1.0 mm —
Temperature na Operasyon 0 °C to 85 °C (commercial) 0C to +85C (Commercial)
High-Speed I/O Support True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps —
Programmable Logic Type Loadable PLD (in-system programmable) —
Embedded Memory Embedded System Blocks (ESB) configurable as dual-port RAM/ROM —
PLLs Up to 4 —
Uri ng Pagpapasok Surface Mount —
Tindminan RoHS [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status]
Product Family — APEX II
Maximum System Gates — 1,650,000
Maximum RAM Bits — 422,976
User I/O Count — 492
Packhaging — 672-ball FCBGA (FineLine BGA)
Supply Voltage (Core) — 1.5 V
LVDS Data Rate — 1 Gbps per channel (True-LVDS)
I/O Standards Supported — LVDS, LVPECL, PCML, HyperTransport
Speed Grade — -7
Configuration Mode — Passive Serial, Passive Parallel, JTAG
Embedded System Blocks (ESB) — Yes - RAM, ROM, CAM, multiplier support

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