EP2A25F672I-9 vs EP2A25F672C8 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP2A25F672I-9 sa pamamagitan ng Intel at EP2A25F672C8 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP2A25F672I-9 EP2A25F672C8
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family APEX II APEX II (EP2A25)
Logic Elements (typical) 25,000 —
Maximum System Gates [DATA_NEEDED: maximum system gates] 40,960
Embedded System Blocks (ESB) Memory 1,125 Kbits —
Maximum User I/O Pins [DATA_NEEDED: maximum user I/O pins] —
Number of PLLs 4 —
Process Technology 0.18 µm CMOS 0.15 microm CMOS, 8-layer copper interconnect
Core Voltage 1.5 V / 1.8 V (speed-grade dependent) —
Operating Temperature Grade Industrial (-40 °C to +100 °C junction) —
Speed Grade -9 C8
Packhaging 672-pin FCBGA (FineLine BGA) 672-FBGA (FineLine BGA, 27x27 mm, 1.0 mm pitch)
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount
Level ng Sensitivity sa Asid ng Moisture (MSL) 3 (per Vyrian listing) —
Peak Reflow Temperature 220 °C (per Vyrian listing) —
Configuration Method JTAG / serial configuration EPROM —
Supported I/O Standards LVTTL, LVCMOS, LVDS, PCI —
Tindminan RoHS [DATA_NEEDED: RoHS status] Non-compliant (legacy product)
Legacy Status Obsolete - consult Altera / Intel FPGA archive for documentation —
Logic Elements — 25,000 (typical gates)
Macrocells / Embedded Logic — 2,432 macros
User I/O Count — 492
Propagation Delay (tpd) — 1.69 ns
Temperature na Operasyon — 0 C to 85 C (commercial)
I/O Standards Supported — LVTTL, LVCMOS, PCI-X, GTL+, SSTL-2/3, HSTL, LVDS, LVPECL
LVDS Data Rate — 1 Gbps
PLL Count — 4
Embedded Memory — ESB blocks (dual-port RAM, FIFO, CAM, ROM)
I/O Banks — 16

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita