EP2A40B724I-9 vs EP2A40B724C9N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A40B724I-9 sa pamamagitan ng Altera at EP2A40B724C9N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2A40B724I-9 | EP2A40B724C9N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | APEX II | APEX II |
| Logic Elements | 40,000 (typical) | — |
| Logic Cells | 38400 | — |
| Embedded Memory Bits | 655360 | — |
| Maximum User I/O | 540 (per EP2A40B724 family) | — |
| Packhaging | 724-ball FCBGA / FineLine BGA | 724-ball FCBGA (Fine-pitch Chip-Scale BGA) |
| Package Code | B724 | — |
| Temperature Grade | Industrial ('I' suffix) | — |
| Temperature ng Junction na Operasyon | -40 C to +100 C (industrial) | — |
| Speed Grade | -9 (per APEX II speed bin) | — |
| Peak Reflow Temperature | 220 C | — |
| Core Voltage | 1.5 V (typical APEX II) | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, SSTL | — |
| Configuration Interface | JTAG, Passive Serial | — |
| PLL | On-chip (per APEX II architecture) | — |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | — |
| Level ng MSL | [DATA_NEEDED: msl level] | — |
| Series | — | EP2A40 |
| Device Type | — | FPGA (Field-Programmable Gate Array) |
| System Gates | — | 1,500,000 |
| Logic Elements / Cells | — | 38,400 |
| Maximum Frequency | — | 366 MHz |
| Propagation Delay | — | 2.05 ns |
| Process Technology | — | 0.15 µm CMOS |
| Core Supply Voltage | — | 1.5 V |
| User I/O Count | — | 536 |
| Terminal Pitch | — | 1.270 mm |
| Number of Terminals | — | 724 |
| Terminal Form | — | Ball |
| Output Function | — | Macrocells |
| Operating Temperature Grade | — | Industrial (OTHER / per datasheet) |
| Uri ng Pagpapasok | — | Surface Mount |