EP2A40F672C6N vs EP2A40F672C7N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP2A40F672C6N sa pamamagitan ng Intel at EP2A40F672C7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP2A40F672C6N EP2A40F672C7N
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family APEX II APEX II
Logic Elements 40,000 —
Maximum System Gates 1,125,000 —
Embedded RAM Bits 442,368 —
Embedded System Blocks (ESBs) 160 —
Maximum User I/O Pins [DATA_NEEDED: maximum user I/O count] —
Core Voltage 1.5 V 1.5 V
I/O Standards Supported LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V —
Packhaging 672-ball FineLine BGA 672-ball FC-FBGA (FineLine BGA), S-PBGA-B672, 27 x 27 mm, 1.0 mm pitch
Temperature na Operasyon Commercial (0C to +85C) 0 °C to 85 °C (commercial, 'C' grade)
Speed Grade C6 (per part number suffix) 7
Configuration Methods Passive Serial, Passive Parallel, JTAG —
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] —
Process Technology SRAM-based, 0.18 um (per family datasheet) 0.15 µm CMOS, all-layer copper, up to 8 metal layers
PLL Count [DATA_NEEDED: PLL count] —
Logic Elements / Cells — 38,400
System Gates — 1.5 M
Maximum User I/Os — 492
Propagation Delay (tpd) — 1.55 ns
Internal Performance — 562 MHz
MultiVolt I/O Support — 1.5 V / 1.8 V / 2.5 V / 3.3 V / 5.0 V
Logic Family — CMOS
Lead-Free / RoHS — Yes (N suffix)
Configuration Modes — Passive Serial, Passive Parallel, JTAG

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