EP2A40F672C7 vs EP2A40F672C9 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP2A40F672C7 sa pamamagitan ng Intel at EP2A40F672C9 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP2A40F672C7 EP2A40F672C9
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Huling Pagbili
Family APEX II APEX II
Logic Elements 38,400 —
System Gates 1,500,000 1.5 M
Macro Cells 2,560 —
Maximum User I/O 492 —
Process Technology 0.15 µm CMOS, all-layer copper, up to 8 metal layers 0.15 µm all-layer copper, up to 8 metal layers
Core Voltage 1.5 V 1.5 V
I/O Voltage Support 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) —
Pin-to-Pin Delay 1.55 ns (C7 speed grade) —
Maximum Internal Frequency 562 MHz —
High-Speed Interface 1 Gbps True-LVDS, LVPECL, PCML, HyperTransport —
PLLs 4 —
Packhaging 672-ball FC-FBGA (FineLine BGA) 672-BBGA, FC-FBGA (FineLine)
Package Dimensions 27 x 27 mm, 1.0 mm pitch —
Uri ng Pagpapasok Surface Mount Surface Mount
Operating Temperature Grade Commercial (per 'C' suffix in speed grade) —
Tindminan RoHS Compliant [DATA_NEEDED: RoHS status]
Lead-Free Yes —
Device Family — APEX II PLD
Logic Elements / Cells — 38,400
Macros — 2,560
User I/Os — 492
Bilang ng Pins — 672
Package Size — 27 mm × 27 mm, 1 mm ball pitch
Logic Family — CMOS
Propagation Delay — 1.55 ns
Internal Speed Grade — 366 MHz
Temperature na Operasyon — 0 °C to 85 °C (commercial)
I/O Standards Supported — True-LVDS, LVPECL, PCML, HyperTransport

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