EP2A40F672C7 vs EP2A40F672C9 比較
詳細並排比較 EP2A40F672C7 由 Intel 與 EP2A40F672C9 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2A40F672C7 | EP2A40F672C9 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Family | APEX II | APEX II |
| Logic Elements | 38,400 | — |
| System Gates | 1,500,000 | 1.5 M |
| Macro Cells | 2,560 | — |
| Maximum User I/O | 492 | — |
| Process Technology | 0.15 µm CMOS, all-layer copper, up to 8 metal layers | 0.15 µm all-layer copper, up to 8 metal layers |
| Core Voltage | 1.5 V | 1.5 V |
| I/O Voltage Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) | — |
| Pin-to-Pin Delay | 1.55 ns (C7 speed grade) | — |
| Maximum Internal Frequency | 562 MHz | — |
| High-Speed Interface | 1 Gbps True-LVDS, LVPECL, PCML, HyperTransport | — |
| PLLs | 4 | — |
| 封裝 | 672-ball FC-FBGA (FineLine BGA) | 672-BBGA, FC-FBGA (FineLine) |
| Package Dimensions | 27 x 27 mm, 1.0 mm pitch | — |
| 安裝類型 | Surface Mount | Surface Mount |
| Operating Temperature Grade | Commercial (per 'C' suffix in speed grade) | — |
| RoHS 狀態 | Compliant | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes | — |
| Device Family | — | APEX II PLD |
| Logic Elements / Cells | — | 38,400 |
| Macros | — | 2,560 |
| User I/Os | — | 492 |
| 腳位數 | — | 672 |
| Package Size | — | 27 mm × 27 mm, 1 mm ball pitch |
| Logic Family | — | CMOS |
| Propagation Delay | — | 1.55 ns |
| Internal Speed Grade | — | 366 MHz |
| 工作溫度 | — | 0 °C to 85 °C (commercial) |
| I/O Standards Supported | — | True-LVDS, LVPECL, PCML, HyperTransport |