EP2A70B724C7ES vs EP2A70B724C8N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A70B724C7ES sa pamamagitan ng Altera at EP2A70B724C8N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP2A70B724C8N - APEX II FPGA, 3M Gates, 724-FCBGA | Altera / Intel
EP2A70B724C8N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP2A70B724C7ES | EP2A70B724C8N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Huling Pagbili |
| Family | APEX II | FPGA (PLD) |
| Typical Gates | 3,000,000 (3M) | — |
| Logic Elements (Cells) | 67,200 | — |
| Maximum Operating Frequency | 420 MHz | — |
| Process Technology | 0.15 µm | 0.15 um CMOS, SRAM-based |
| Core Voltage | 1.5 V | — |
| Packhaging | 724-pin FCBGA | — |
| User I/O Pins | 540 | — |
| Speed Grade | C7 | — |
| Temperature Grade | Commercial (C) | — |
| Uri ng Memory | Embedded System Block (ESB) | — |
| PLLs | Up to 8 | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | — |
| Programming Interface | JTAG / ByteBlaster | — |
| Device Marking Suffix | ES (Engineering Sample) | — |
| Series | — | APEX II (EP2A70) |
| System Gates | — | 3,000,000 (3 M) |
| Logic Elements / Cells | — | 67,200 |
| Macrocells | — | 16 |
| Product Terms | — | 32 |
| Propagation Delay | — | 2.49 ns |
| Maximum Internal Clock Frequency | — | 281 MHz |
| Maximum Clock Frequency (fMAX) | — | 1694.91 MHz |
| Core Supply Voltage | — | 1.5 V |
| Architecture | — | PLA-type / LUT-based |
| Package Type | — | FCBGA-724 (square) |
| Number of Pins / Balls | — | 724 |
| Terminal Pitch | — | 1.270 mm |
| Maximum User I/O | — | 536 |