EP2AGX125EF35I5N vs EP2AGX125EF35C4G Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2AGX125EF35I5N sa pamamagitan ng Intel at EP2AGX125EF35C4G sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP2AGX125EF35I5N - Arria II GX FPGA 118K LE, 6x 3.125G Transceivers | Intel
EP2AGX125EF35I5N ✓ NakahandaIntel
EP2AGX125EF35C4G - Arria II GX FPGA, 118K LEs, 1152-FCBGA | Intel
EP2AGX125EF35C4G ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP2AGX125EF35I5N | EP2AGX125EF35C4G |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Huling Pagbili |
| Family | Arria II GX | Arria II GX |
| Device Logic Elements | 118,143 | — |
| Combinational Logic Blocks (CLBs) | 124,100 | — |
| Logic Array Blocks (LABs) | 4,964 | — |
| User I/Os | 452 | — |
| Embedded Memory | 8.4 Mbit (M9K + MLAB) | — |
| DSP Blocks (18x18 Multipliers) | 252 | — |
| Transceivers | 6 (up to 3.125 Gbps) | — |
| PLLs | 4 | — |
| Process Technology | 40 nm CMOS | 40 nm |
| Core Supply Voltage | 0.9 V | — |
| Speed Grade | I5 (industrial, fastest) | C4 |
| Temperature na Operasyon | -40C to +100C (industrial) | 0C to +85C (Commercial) |
| Packhaging | 1152-ball FC-FBGA, 35 x 35 mm | 1152-ball FC-FBGA (Flip-Chip) |
| Uri ng Pagpapasok | Surface Mount (flip-chip BGA) | Surface Mount |
| Lead-Free / RoHS | Lead-Free per MS-034 | — |
| PCI Express Hard IP | Gen1 x1/x4 endpoint | Gen1/Gen2 x1/x4/x8 |
| Configuration Schemes | AS, PS, JTAG, FPP | — |
| Logic Elements | — | 118,143 |
| Embedded Memory Bits | — | 8,315,904 |
| Memory Blocks (M9K) | — | [DATA_NEEDED: M9K count] |
| Hardware Multipliers (18x18) | — | 452 |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |
| Transceiver Channels | — | 12 |
| Maximum Transceiver Data Rate | — | 6.375 Gbps |
| Core Voltage | — | 0.9 V |
| User I/O Banks | — | [DATA_NEEDED: I/O bank count] |
| Maximum User I/O | — | [DATA_NEEDED: max user I/O count] |
| Configuration Method | — | SRAM-based, PS/FPP/JTAG |
| Tindminan RoHS | — | Compliant |
| Lead-Free | — | Yes |