EP2AGZ300FF35I3G vs EP2AGX190FF35I3G Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2AGZ300FF35I3G sa pamamagitan ng Intel at EP2AGX190FF35I3G sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP2AGX190FF35I3G - Arria II GX FPGA 190K LE | Intel | Altera
EP2AGX190FF35I3G ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP2AGZ300FF35I3G | EP2AGX190FF35I3G |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Huling Pagbili |
| Family | Arria II GZ | Arria II GX |
| Logic Elements (LE) | 300000 | 181,165 |
| Number of User I/O | 554 (maximum) | — |
| Number of Transceivers | 8 | — |
| Transceiver Data Rate | Up to 6.375 Gbps | — |
| Process Node | 40 nm | 40 nm |
| Temperature na Operasyon | -40C to +100 C (I3 industrial) | -40 °C to +100 °C (industrial, suffix I) |
| Packhaging | 1152-ball FBGA (FF35) | 1152-ball FC-FBGA (FF35), 35 mm body |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (flip-chip BGA) |
| Volte ng Pagbibigay | [DATA_NEEDED: core and I/O supply voltage values] | — |
| Embedded Memory (Mbits) | 16.4 | — |
| DSP Blocks | [DATA_NEEDED: number of DSP blocks] | — |
| PLLs | [DATA_NEEDED: number of PLLs] | [DATA_NEEDED: PLL count] |
| Memory Interfaces | DDR3, QDRII+, RLDRAM II | — |
| Configuration Method | Serial, Parallel, JTAG | — |
| Tindminan RoHS | Compliant | Compliant (suffix G) |
| Level ng MSL | 3 (168 hours) | — |
| Lead-Free | Yes | Yes |
| Adaptive Logic Modules (ALM) | — | [DATA_NEEDED: ALM count] |
| User I/O Pins | — | 612 |
| Embedded Memory (bits) | — | 10,177,536 |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Transceivers | — | 8 high-speed transceiver channels (multi-gigabit) |
| Embedded Multipliers | — | [DATA_NEEDED: 18x18 multiplier count] |
| Core Voltage | — | 0.9 V |
| I/O Voltage Standards | — | 1.2 V to 3.3 V (LVTTL, LVCMOS, LVDS, HSTL, SSTL) |
| Speed Grade | — | 3 |
| Ball Pitch | — | [DATA_NEEDED: 1.0 mm (typical for FF35)] |
| Programming Toolchain | — | Quartus II / Quartus Prime |