EP2C50F672C7 vs EP2C35F672C8 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP2C50F672C7 sa pamamagitan ng Altera at EP2C35F672C8 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP2C50F672C7 EP2C35F672C8
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili NRND
Family Cyclone II Cyclone II
Logic Elements (LE) 50,528 —
Embedded Memory Bits 594,432 bits —
Embedded Memory Blocks 250 M4K blocks (4 Kbit each) —
Embedded 18x18 Multipliers 86 (150 per device family datasheet figure) —
User I/O Pins 450 —
Phase-Locked Loops (PLL) 4 —
Global Clock Networks 16 —
Process Technology 90 nm CMOS with low-k dielectric 90 nm
Core Voltage (VCCINT) 1.2 V 1.15 V - 1.25 V
I/O Voltage (VCCIO) 1.5 V / 1.8 V / 2.5 V / 3.0 V / 3.3 V (per bank) —
Packhaging 672-ball FineLine BGA (FBGA-672) 672-BGA (FineLine BGA, 1.0 mm pitch)
Speed Grade -7 C8 (commercial, 8 ns pin-to-pin)
Temperature Grade Commercial (0C to +85C junction) —
Configuration Modes Passive Serial (PS), Active Serial (AS), JTAG Active Serial (AS), Passive Serial (PS), JTAG
Lead-Free / RoHS Lead-Free / RoHS compliant per Heisener listing —
Logic Elements (LEs) — 33,216
Total RAM Bits — 483,840
Embedded Multipliers (18x18) — 35
User I/O Pins (max) — 475
Number of PLLs — 4
Operating Temperature (Commercial) — 0C to +85C
Memory Interface Support — DDR, DDR2, SDR SDRAM
I/O Standards — LVTTL, LVCMOS, SSTL, LVDS, RSDS, mini-LVDS, PPDS
Uri ng Pagpapasok — Surface Mount
Tindminan RoHS — Compliant (lead-free package)

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