EP2S15F484C5N vs EP2S15F484C4 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2S15F484C5N sa pamamagitan ng Intel at EP2S15F484C4 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2S15F484C5N | EP2S15F484C4 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Presyo ng Yunit (USD) | — | $205.00 |
| Family | Stratix II | Stratix II |
| Logic Elements (LEs) | 15,600 | 15,600 |
| Embedded RAM | 419 Kbits | — |
| Maximum User I/O | 342 | 342 |
| DSP Blocks | [DATA_NEEDED: DSP block count] | Yes (integrated multiplier-accumulators) |
| Process Technology | 90 nm | 90 nm CMOS |
| Packhaging | 484-ball FineLine BGA (FBGA) | 484-FBGA (FBGA-484) |
| Speed Grade | C5 | C4 (-4, mid-tier) |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | — |
| Configuration Modes | AS, PS, JTAG | — |
| Supply Voltage - Core (VCCINT) | [DATA_NEEDED: VCCINT nominal] | — |
| Supply Voltage - I/O (VCCIO) | [DATA_NEEDED: VCCIO nominal] | — |
| PLLs | [DATA_NEEDED: PLL count] | — |
| External Memory Support | DDR/DDR2 SDRAM, QDR II SRAM | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant (lead-free FBGA package) |
| Uri ng Pagpapasok | Surface Mount | — |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Adaptive Logic Modules (ALMs) / CLBs | — | 6,240 |
| Embedded Memory (Bits) | — | 419,328 |
| Package Dimensions | — | 23 mm x 23 mm |
| Ball Pitch | — | 1.0 mm |
| Core Performance | — | Up to 717 MHz |
| Temperature Grade | — | Commercial (C): 0 C to +85 C junction |
| Supply Voltage (Core) | — | [DATA_NEEDED: VCCINT nominal] |
| I/O Standards Supported | — | LVDS, LVTTL, LVCMOS, SSTL, HSTL |
| External Memory Interface | — | DDR, DDR2, QDR SRAM |
| Configuration Method | — | Serial/parallel, JTAG |