EP2S15F672C3 vs EP2S15F672C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2S15F672C3 sa pamamagitan ng Intel at EP2S15F672C5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2S15F672C3 | EP2S15F672C5N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | Stratix II | Stratix II |
| Logic Elements | 15,600 | 15,600 |
| Embedded Memory (bits) | 419,328 | 419,328 |
| DSP Blocks (18-bit multipliers) | 156 | — |
| Maximum User I/O | 366 | — |
| Core Voltage | 1.2 V | — |
| Process Technology | 90 nm CMOS | — |
| Maximum Internal Frequency | [DATA_NEEDED: max internal clock MHz] | 640 MHz |
| Packhaging | 672-ball FC-FBGA | 672-BBGA / FBGA-672 |
| Uri ng Pagpapasok | Surface Mount | — |
| Operating Temperature Grade | Commercial (C3 suffix) | — |
| Speed Grade | C3 (third commercial speed bin) | -C5 |
| PLLs | [DATA_NEEDED: number of PLLs] | — |
| Global Clock Networks | [DATA_NEEDED: number of global clocks] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | RoHS Compliant |
| Level ng MSL | [DATA_NEEDED: moisture sensitivity level] | — |
| Series | — | Altera Stratix II |
| Logic Array Blocks (LABs) | — | 780 |
| Configurable Logic Blocks (CLBs) | — | 6,240 |
| User I/O Pins | — | 366 |
| Package Dimensions | — | 35 x 35 mm |
| Ball Pitch | — | 1.0 mm |
| Temperature na Operasyon | — | 0C to +85C (commercial) |
| Lead-Free (Pb-Free) | — | Yes |