EP2S15F672C5 vs EP2S15F672C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2S15F672C5 sa pamamagitan ng Intel at EP2S15F672C5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2S15F672C5 | EP2S15F672C5N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Family | Stratix II | Stratix II |
| Series | EP2S15 | Altera Stratix II |
| Logic Elements | 15,600 | 15,600 |
| CLBs | 6,240 | — |
| Memory Bits | 419,328 | — |
| Maximum User I/O | 366 | — |
| Operating Frequency (max) | 640 MHz | — |
| Speed Grade | -5 (mid-tier) | -C5 |
| Package Type | 672-ball FineLine BGA (FBGA) | — |
| Package Dimensions | 27 mm x 27 mm | 35 x 35 mm |
| Ball Pitch | 1 mm | 1.0 mm |
| Process Technology | 90 nm CMOS | — |
| Voltage - Supply (VCCINT) | [DATA_NEEDED: VCCINT nominal] | — |
| Temperature na Operasyon | Commercial (0C to +85C) | 0C to +85C (commercial) |
| Configuration Method | Passive Serial / Fast Passive Parallel / JTAG | — |
| Tindminan RoHS | Compliant (legacy lead-free version exists) | RoHS Compliant |
| Uri ng Pagpapasok | Surface Mount | — |
| Logic Array Blocks (LABs) | — | 780 |
| Configurable Logic Blocks (CLBs) | — | 6,240 |
| Embedded Memory (bits) | — | 419,328 |
| User I/O Pins | — | 366 |
| Packhaging | — | 672-BBGA / FBGA-672 |
| Maximum Internal Frequency | — | 640 MHz |
| Lead-Free (Pb-Free) | — | Yes |