EP2S30F672I4 vs EP2S30F672C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2S30F672I4 sa pamamagitan ng Intel at EP2S30F672C5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2S30F672I4 | EP2S30F672C5N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Series | Stratix II | Stratix II |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements | 33880 | 33,880 |
| Logic Array Blocks (LABs) | 1694 | 1694 |
| Total RAM Bits | 1369728 | — |
| Number of I/O | 500 | — |
| DSP Blocks | 12 (per datasheet, family range) | [DATA_NEEDED: DSP block count] |
| Number of PLLs | 6 | 4 |
| Voltage - Supply | 1.2 V core, separate I/O bank VCCIO | — |
| Temperature na Operasyon | -40C to +100C (Industrial) | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Packhaging / Kaso | 672-BBGA, FCBGA (FBGA-672) | — |
| Package Dimensions | 35 x 35 mm | — |
| Ball Pitch | 1.0 mm | — |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Configuration | JTAG, serial, parallel (Stratix II scheme) | — |
| Level ng MSL | 3 (per JEDEC J-STD-020) | — |
| Tindminan RoHS | [DATA_NEEDED: confirm RoHS compliance on part label] | — |
| Family Name | — | Stratix II |
| Embedded Memory (bits) | — | 1,369,728 |
| User I/O Count | — | 500 |
| Packhaging | — | 672-ball FBGA (FineLine BGA) |
| Speed Grade | — | C5 (-5 commercial) |
| Supply Voltage (Core) | — | [DATA_NEEDED: core VCC value] |
| Hanay ng Temperature na Operasyon | — | Commercial (0C to +85C) |
| Global Clock Networks | — | 16 |
| Configuration Method | — | Serial / Passive Parallel / Fast Passive Parallel |
| Lead-Free / RoHS | — | Yes (N suffix) |
| Architecture | — | Adaptive Logic Module (ALM) |
| Multipliers | — | [DATA_NEEDED: 18x18 multiplier count] |