EP2S60F1020I4N vs EP2S60F1020C4N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2S60F1020I4N sa pamamagitan ng Intel at EP2S60F1020C4N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2S60F1020I4N | EP2S60F1020C4N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | Stratix II | Stratix II |
| Family | Stratix II FPGA | Stratix II (EP2S60) |
| Logic Elements (LE) | 60,440 | — |
| Embedded Memory Bits | 2,544,192 | — |
| Maximum User I/O | 718 | — |
| Number of I/O Banks | 32 | — |
| DSP Blocks (18x18 multipliers) | 36 | — |
| PLLs | 12 | — |
| Core Voltage | 1.2 V | 1.2 V |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Packhaging | 1020-ball FCBGA (33 x 33 mm) | 1020-ball FC-FBGA (Fine-pitch Chip-Scale BGA) |
| Temperature na Operasyon | -40C to +100C (Industrial) | — |
| Speed Grade | -4 | — |
| Configuration Scheme | PS, PPS, PPA, FPP, JTAG | — |
| Embedded Transceiver Channels | 12 channels up to 6.375 Gbps | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Tindminan RoHS | unknown | EU RoHS compliant with exemption (per Arrow listing) |
| Logic Elements | — | 60,440 |
| Adaptive Logic Modules (ALMs) | — | 30,220 (approx.) |
| Logic Array Blocks (LABs) | — | 3,022 |
| Embedded Memory (bits) | — | 2,544,192 |
| Embedded Memory Blocks | — | M512/M4K/M-RAM TriMatrix memory |
| DSP Blocks (18-bit x 18-bit) | — | Up to 48 (24 per DSP block column pair typical) |
| User I/Os | — | 718 |
| Maximum Core Frequency | — | 711.24 MHz (per Arrow listing) |
| Operating Temperature Grade | — | Commercial (C4 suffix indicates commercial, speed grade 4) |
| Configuration Modes | — | Passive Serial, Fast Passive Parallel, JTAG |
| PLLs / Clock Networks | — | Yes - on-chip PLLs and global clock networks |