EP2S60F672C4N vs EP2S60F672C4 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2S60F672C4N sa pamamagitan ng Intel at EP2S60F672C4 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2S60F672C4N | EP2S60F672C4 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | Stratix II | Stratix II |
| Process Technology | 90 nm | 90 nm |
| Logic Elements (LE) | 60,440 | 60440 |
| Adaptive Logic Modules (ALM) | 24,176 | — |
| Embedded Memory (bits) | 2,544,192 | — |
| Embedded Multiplier Blocks | [DATA_NEEDED: 9x9 multiplier count] | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | [DATA_NEEDED: DSP block count per Stratix II variant] |
| Maximum User I/O | 492 | — |
| Core Voltage | 1.2 V | 1.2 V (typical) |
| Maximum Fabric Clock | 711.24 MHz | — |
| Packhaging | 672-pin FC-FBGA | 672-BBGA, FCBGA |
| Package Type | FineLine Ball-Grid Array | — |
| Speed Grade | C4 (commercial) | C4 |
| Temperature na Operasyon | 0C to +85C (commercial) | 0C to +85C (commercial) |
| Configuration Method | JTAG, Fast Passive Parallel, Active Serial | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | 3 | [DATA_NEEDED: not in provided data] |
| Lead-Free / RoHS | Yes (lead-free finish) | — |
| Embedded Memory Bits | — | 2544192 |
| Logic Array Blocks (LAB) | — | 3022 |
| User I/Os | — | 492 |
| Tindminan RoHS | — | [DATA_NEEDED: not confirmed in provided data] |
| Lead-Free | — | [DATA_NEEDED: not confirmed in provided data] |