EP3C5E144A7N vs EP3C5E144I7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3C5E144A7N sa pamamagitan ng Altera at EP3C5E144I7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP3C5E144A7N | EP3C5E144I7N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | Cyclone III | — |
| Logic Elements (LE) | 5,136 | 5,136 |
| Total Memory Bits | 423,936 bits (414 Kbits) | — |
| Embedded Memory Blocks | 46 x M9K (9 Kbit each) | — |
| Embedded 18x18 Multipliers | 23 | 23 |
| User I/O Pins | 94 | — |
| Number of I/O Banks | 4 | — |
| Number of PLLs | 4 | — |
| Core Voltage (VCCINT) | 1.2 V | — |
| I/O Bank Voltage (VCCIO) | Per-bank, supports 1.2 V to 3.3 V | — |
| Packhaging | 144-LQFP Exposed Pad (EQFP, 22x22 mm) | 144-pin EQFP (Enhanced QFP) with exposed pad |
| Speed Grade | 7 | — |
| Temperature Grade | Commercial (0C to +85C junction) | — |
| Process Technology | 65 nm low-k dielectric | 60 nm low-k |
| Configuration Modes | AS, PS, JTAG, Fast Passive Parallel | — |
| Design Toolchain | Quartus II / Quartus Prime | — |
| Supported I/O Standards | LVDS, SSTL, LVTTL, PCI, LVCMOS | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | Compliant (per DigiKey product page) | Compliant |
| Family | — | Cyclone III |
| Embedded Memory Bits | — | 423,936 |
| PLLs | — | 4 |
| Maximum User I/O Pins | — | 94 |
| Core Voltage | — | 1.2 V |
| Maximum Internal Clock Frequency | — | 437.5 MHz |
| Package Dimensions | — | 20 mm x 20 mm, 0.4 mm pitch |
| Temperature na Operasyon | — | -40 °C to +100 °C (industrial) |
| Configuration Interface | — | JTAG (IEEE 1149.1), passive serial, active serial |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |