EP3C5E144A7N vs EP3C5E144I7N 比較
詳細並排比較 EP3C5E144A7N 由 Altera 與 EP3C5E144I7N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP3C5E144A7N | EP3C5E144I7N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Series | Cyclone III | — |
| Logic Elements (LE) | 5,136 | 5,136 |
| Total Memory Bits | 423,936 bits (414 Kbits) | — |
| Embedded Memory Blocks | 46 x M9K (9 Kbit each) | — |
| Embedded 18x18 Multipliers | 23 | 23 |
| User I/O Pins | 94 | — |
| Number of I/O Banks | 4 | — |
| Number of PLLs | 4 | — |
| Core Voltage (VCCINT) | 1.2 V | — |
| I/O Bank Voltage (VCCIO) | Per-bank, supports 1.2 V to 3.3 V | — |
| 封裝 | 144-LQFP Exposed Pad (EQFP, 22x22 mm) | 144-pin EQFP (Enhanced QFP) with exposed pad |
| Speed Grade | 7 | — |
| Temperature Grade | Commercial (0C to +85C junction) | — |
| Process Technology | 65 nm low-k dielectric | 60 nm low-k |
| Configuration Modes | AS, PS, JTAG, Fast Passive Parallel | — |
| Design Toolchain | Quartus II / Quartus Prime | — |
| Supported I/O Standards | LVDS, SSTL, LVTTL, PCI, LVCMOS | — |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | Compliant (per DigiKey product page) | Compliant |
| Family | — | Cyclone III |
| Embedded Memory Bits | — | 423,936 |
| PLLs | — | 4 |
| Maximum User I/O Pins | — | 94 |
| Core Voltage | — | 1.2 V |
| Maximum Internal Clock Frequency | — | 437.5 MHz |
| Package Dimensions | — | 20 mm x 20 mm, 0.4 mm pitch |
| 工作溫度 | — | -40 °C to +100 °C (industrial) |
| Configuration Interface | — | JTAG (IEEE 1149.1), passive serial, active serial |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |