EP3SE110F1152C3 vs EP3SE110F1152C3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SE110F1152C3 sa pamamagitan ng Altera at EP3SE110F1152C3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP3SE110F1152C3N - Stratix III E FPGA, 107.5K LE, FC-FBGA-1152 | Intel
EP3SE110F1152C3N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP3SE110F1152C3 | EP3SE110F1152C3N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Huling Pagbili |
| Family | Stratix III E | Stratix III E |
| Logic Elements | 107,500 | — |
| Logic Array Blocks (LABs) | 4,300 | 4,300 |
| Adaptive Logic Modules (ALMs) | 43,040 | — |
| Total Block Memory Bits | 8,936,448 | — |
| User I/Os | 744 | 744 |
| Internal Operating Frequency (max) | 800 MHz | — |
| Core Supply Voltage | 0.9 V | 1.1 V nominal |
| Temperature na Operasyon | 0 C to 85 C | 0 °C to 85 °C (commercial) |
| Packhaging | 1152-BBGA, FCBGA | — |
| Uri ng Pagpapasok | Surface Mount (Flip-Chip BGA) | Surface Mount |
| Tindminan RoHS | Compliant | — |
| Level ng MSL | [DATA_NEEDED: moisture sensitivity level] | — |
| Process Node | 40 nm | — |
| Speed Grade | C3 (commercial, slower speed grade) | C3 |
| Series | — | Stratix III |
| Logic Elements (LE) | — | 107,500 |
| Total RAM Bits | — | 8,936,448 |
| Operating Frequency (max) | — | 500 MHz |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O supply range] |
| Process Technology | — | 65 nm TSMC |
| Package Type | — | FC-FBGA-1152 (flip-chip BGA) |
| Style ng Pagpapasok | — | SMD/SMT (Tray) |
| DSP Blocks | — | Yes (embedded multipliers) |
| Uri ng Memory | — | M9K and M144K block RAM |
| External Memory Support | — | DDR/DDR2/DDR3 with read/write leveling |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |
| RoHS | — | [DATA_NEEDED: RoHS status] |
| Lead-Free | — | Yes (per Altera/Intel datasheet family convention) |