EP3SE260F1517I4LN vs EP3SE260F1517I4L Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SE260F1517I4LN sa pamamagitan ng Intel at EP3SE260F1517I4L sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP3SE260F1517I4LN - 260K LE Stratix III E FPGA, 1517-FCBGA | Intel
EP3SE260F1517I4LN ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP3SE260F1517I4LN | EP3SE260F1517I4L |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Aktibo |
| Logic Elements | 255,000 | 255,000 |
| Embedded Memory Bits | 16,672,768 bits (~2,044 KBytes) | — |
| Logic Array Blocks (LABs) | 10,200 | — |
| User I/O Count | 976 | — |
| Packhaging | 1517-ball FCBGA (40 mm x 40 mm, 1.0 mm pitch) | — |
| Process Technology | 40 nm CMOS | 65 nm CMOS |
| Family | Stratix III E (Enhanced) | Stratix III Enhanced (E) |
| Speed Grade | I4 (industrial, 4th tier) | I4 |
| Power Option | L (low-power) | — |
| Temperature na Operasyon | -40C to +100C (case, industrial) | -40C to +100C (Industrial) |
| Lead-Free / RoHS | Yes (N suffix) | Yes (L suffix) |
| Transceivers | Stratix III E family supports up to 24 transceivers up to 8.5 Gbps | — |
| DSP Blocks (18x18 multipliers) | Up to 384 (family-level, device-specific count not in provided data) | — |
| Partial Reconfiguration | Supported | — |
| Memory Interface Support | DDR3, DDR2, QDR II+ (hardened PHY) | — |
| Configuration Scheme | Active Serial (AS), Passive Serial (PS), Fast Passive Parallel (FPP), JTAG | — |
| Series | — | Stratix III |
| Embedded Memory | — | 16,672,768 bits (16.6 Mbits) |
| Maximum User I/O | — | 976 |
| Package Type | — | 1517-BBGA, FCBGA |
| Package Dimensions | — | 40 mm x 40 mm (BGA1517, 39x39, 1.0 mm pitch) |
| Uri ng Pagpapasok | — | Surface Mount |
| Temperature Grade | — | Industrial |
| Supply Voltage (Core) | — | [DATA_NEEDED: core voltage] |
| DSP Blocks (18x18 Multipliers) | — | 768 |
| Configuration Method | — | JTAG, Passive Serial, Fast Passive Parallel |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |
| Tindminan RoHS | — | Compliant |