EP3SE260H780I3N vs EP3SE260H780C3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SE260H780I3N sa pamamagitan ng Intel at EP3SE260H780C3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP3SE260H780I3N - Stratix III E FPGA 255K LE 780-FCBGA | Intel
EP3SE260H780I3N ⚠ Huling PagbiliIntel
EP3SE260H780C3N - Stratix III E FPGA, 255K LE, 780-BGA | Intel / Altera
EP3SE260H780C3N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP3SE260H780I3N | EP3SE260H780C3N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Aktibo |
| Family | Stratix III E | — |
| Logic Elements (LE) | 255,000 | 255,000 |
| Logic Array Blocks (LABs) | 10,200 | — |
| Embedded Memory (bits) | 16,672,768 | 16,672,768 |
| User I/Os | 488 | 488 |
| Operating Frequency (max) | 500 MHz | — |
| Process Technology | 65 nm CMOS | 40 nm CMOS |
| Core Supply Voltage (VCCINT) | 1.1 V | — |
| Bilang ng Pins | 780 | — |
| Packhaging | 780-FBGA (HBGA, FCBGA) | 780-BBGA, FCBGA (H780) |
| Package Code | BGA780 | — |
| Uri ng Pagpapasok | Surface Mount (FCBGA) | Surface Mount |
| Temperature Grade | Industrial (-40C to +100C) | — |
| Speed Grade | 3 (mid) | — |
| Tindminan RoHS | Compliant | Compliant (lead-free 'N' suffix) |
| Lead-Free / Halogen-Free | Lead-Free (per datasheet family) | — |
| Programmable Logic Type | SRAM-based FPGA | — |
| Series | — | Stratix® III E |
| Number of LABs/CLBs | — | 10,200 |
| Number of Pins / Balls | — | 780 |
| Temperature na Operasyon | — | 0 °C to +85 °C (C grade, commercial) |
| Maximum Core Frequency | — | [DATA_NEEDED: maximum core frequency MHz] |
| Supply Voltage (VCCINT) | — | [DATA_NEEDED: VCCINT nominal V] |
| Transceivers | — | [DATA_NEEDED: number of embedded transceivers and max data rate] |
| DSP Blocks | — | [DATA_NEEDED: number of DSP blocks and precision] |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | — | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Configuration Method | — | SRAM-based, configured via JTAG / passive / active serial / fast passive parallel |
| Design Toolchain | — | Altera Quartus II (legacy); Intel Quartus Prime |