EP3SE50F484C2G vs EP3SE50F484C2N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SE50F484C2G sa pamamagitan ng Intel at EP3SE50F484C2N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP3SE50F484C2G | EP3SE50F484C2N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Series | Stratix III E | Stratix III E |
| Number of Logic Elements / Cells | 47,500 | — |
| Number of LABs / CLBs | 1,900 | — |
| Total RAM Bits | 5,760,000 (5,760 Kbit) | — |
| Number of User I/O | 296 | — |
| Packhaging / Kaso | 484-BBGA, FCBGA (FineLine BGA) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Core Voltage Supply | 0.86 V to 1.15 V | — |
| Temperature na Operasyon | 0 °C to +85 °C (TJ) | 0C to +85C (Commercial) |
| Process Technology | 40 nm TSMC low-power CMOS | 65 nm |
| Logic Element Architecture | Adaptive Logic Module (ALM) with 8-input fracturable LUT | — |
| Embedded DSP Blocks | Yes (variable-precision multipliers) | — |
| Transceivers | Multi-gigabit transceivers (selected package pins) | — |
| Memory Interface Support | DDR / DDR2 / DDR3 with hard PHY | — |
| Partial Reconfiguration | Supported | — |
| Configuration Interface | JTAG, Passive Serial, Fast Passive Parallel | — |
| Part Status | Active (Intel catalogue); long-term supply subject to Stratix III lifecycle policy | — |
| Tindminan RoHS | Compliant | Compliant |
| Family | — | Stratix III E FPGA |
| Logic Elements | — | 47,500 |
| Embedded Memory | — | 2,304 Kbits |
| DSP Blocks (18x18) | — | 264 |
| User I/Os | — | 296 |
| LABs/CLBs | — | 1,900 |
| Core Voltage | — | 0.9 V / 1.1 V |
| Internal Frequency | — | 600 MHz |
| Packhaging | — | 484-ball FCBGA (F484, 23x23 mm, 1.0 mm pitch) |
| Lead-Free | — | Yes |