EP3SE50F780C4N vs EP3SE50F780C4LG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SE50F780C4N sa pamamagitan ng Intel at EP3SE50F780C4LG sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP3SE50F780C4LG - 47.5K LE Stratix III E FPGA, 488 I/O, FBGA-780 | Intel
EP3SE50F780C4LG ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP3SE50F780C4N | EP3SE50F780C4LG |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Huling Pagbili |
| Family | Stratix III E | Stratix III E (Enhanced) |
| Logic Elements (LE) | 47,500 | — |
| Embedded Memory Bits | 5,760,000 | — |
| Embedded Memory (M9K/M144K blocks) | 488 (per family datasheet) | — |
| Number of LABs | 1900 | — |
| Maximum User I/Os | 488 | — |
| DSP Blocks (18x18 multipliers) | 432 | [DATA_NEEDED: DSP block count] |
| PLLs | 12 (per family datasheet) | — |
| Maximum Operating Frequency | 717 MHz | — |
| Transceiver Channels | Up to 12 (per family, model-dependent) | — |
| Transceiver Data Rate | Up to 6.375 Gbps (per Stratix III E family) | — |
| Process Node | 40 nm | — |
| Packhaging | 780-Ball FBGA, 29 mm x 29 mm, 1.0 mm pitch | 780-BBGA, FCBGA (FBGA-780, 1.0 mm pitch) |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (SMT) |
| Volte ng Pagbibigay | Core 0.9 V, I/O 1.2 V-3.3 V (multi-rail) | — |
| Temperature na Operasyon | 0C to +85C (C4 commercial grade) | — |
| Configuration Modes | JTAG, Passive Serial, Fast Passive Parallel | — |
| Tindminan RoHS | Lead-free / RoHS compliant | — |
| Level ng MSL | 3 (per JEDEC J-STD-020, FBGA package) | — |
| Hard Memory Controller | DDR2/DDR3 SDRAM (per Stratix III E family) | — |
| Logic Elements | — | 47,500 LE |
| Adaptive Logic Modules (ALMs) | — | 19,000 ALM |
| Embedded Memory | — | 5.49 Mbit |
| User I/Os | — | 488 I/O |
| Number of Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Transceivers | — | [DATA_NEEDED: transceiver count and rate] |
| Process Technology | — | 40 nm TSMC low-power CMOS |
| Speed Grade | — | -4 (fastest commercial) |
| Operating Temperature (Commercial) | — | 0 C to +85 C |
| Core Voltage (VCCINT) | — | 0.9 V / 1.0 V / 1.1 V (programmable) |
| Supply Voltage na Operasyon | — | 1.1 V (logic core nominal) |
| Lead-Free Status | — | Pb-free (LG suffix) |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | — | MSL 3 (per JEDEC J-STD-020) |
| RoHS Compliance | — | Compliant |