EP3SL200H780C4L vs EP3SL200H780I4L Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SL200H780C4L sa pamamagitan ng Intel at EP3SL200H780I4L sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP3SL200H780C4L | EP3SL200H780I4L |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | NRND |
| Manufacturer | Intel (formerly Altera) | — |
| Series | Stratix III | — |
| Device Type | FPGA - Field Programmable Gate Array | — |
| Logic Elements | 200,000 | 200,000 |
| Embedded Memory | 6.5 Mbit | — |
| User I/O Count | 488 | — |
| Package Type | 780-ball FCBGA (FineLine BGA, HBGA) | — |
| Package Code | BGA-780 / PBGA780 / HBGA-780 | — |
| Package Mounting | Surface Mount | — |
| Internal Logic Frequency | up to 717 MHz (per ampheo datasheet brief) | — |
| Speed Grade | -4 (medium performance, commercial) | I4 (Industrial) |
| Temperature na Operasyon | 0C to 85C (commercial) | -40C to +100C (Industrial) |
| Lead-Free / Pb-Free | Yes (L suffix, lead-free) | — |
| Tindminan RoHS | Compliant | Compliant |
| Process Technology | TSMC 40 nm | 65 nm CMOS |
| Configuration Modes | FPP, AS, PS, JTAG | — |
| Family | — | Stratix III L |
| Logic Array Blocks (LABs) | — | 8,000 |
| Embedded Memory (Bits) | — | 10,901,504 |
| Maximum User I/O | — | 488 |
| Core Supply Voltage | — | 0.86 V to 1.15 V |
| Internal Performance | — | 375 MHz |
| Packhaging | — | 780-pin FC-HFBGA (Flip-Chip) |
| Uri ng Pagpapasok | — | Surface Mount |
| Transceivers | — | Up to 24 channels |
| Transceiver Data Rate | — | Up to 6.375 Gbps |
| DSP Blocks | — | 9x9 / 18x18 / 36x36 multipliers |
| Memory Interface Support | — | DDR3, DDR2, DDR, QDR II+, RLDRAM II |
| JTAG Support | — | IEEE Std 1149.1 Boundary-Scan |
| HardCopy Support | — | Compatible (Lattice-style migration path via HardCopy III) |