EP3SL340H1152C2N vs EP3SL340H1152C4L Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SL340H1152C2N sa pamamagitan ng Intel at EP3SL340H1152C4L sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP3SL340H1152C2N - Stratix III L FPGA, 337.5K LE, 1152-BGA | Intel
EP3SL340H1152C2N ⚠ Huling Pagbili
Pagsanggunian na paghahambing
| Parametro | EP3SL340H1152C2N | EP3SL340H1152C4L |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Family | Stratix III L | — |
| Logic Elements | 337,500 | 337,500 |
| Embedded Memory Bits | 18,822,144 | 18,822,144 |
| DSP Blocks (18x18 multipliers) | 744 | — |
| Process Technology | 65 nm CMOS | 65 nm |
| Core Voltage | 0.9 V | — |
| Auxiliary / I/O Supply | 1.1 V | — |
| Maximum Fabric Frequency | 600 MHz | — |
| Packhaging | 1152-Ball FC-HFBGA (flip-chip) | 1152-BBGA, FCBGA (HBGA) |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Lead-Free / RoHS | Lead-free (per distributor listing) | — |
| Operating Temperature Grade | Commercial | — |
| Speed Grade | C2 (moderate) | C4L (L-suffix low power) |
| JTAG Support | IEEE Std 1149.1 Boundary-Scan | — |
| Uri ng Memory | TriMatrix (MLAB + M9K + M144K) | — |
| Series | — | Stratix III L |
| Maximum User I/O | — | 744 |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Embedded 18x18 Multipliers | — | 384 (per family datasheet) |
| Core Voltage (VCCINT) | — | 1.1 V |
| Temperature na Operasyon | — | 0 C to +85 C (commercial) |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS compliance] |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: lead-free status] |
| Configuration Memory | — | SRAM-based, volatile (needs external config device) |
| Maximum Operating Frequency | — | [DATA_NEEDED: per design, ~450 MHz logic per GlobalSpec listing] |
| I/O Standards Supported | — | LVDS, LVTTL, LVCMOS, SSTL, HSTL (per family) |