EP3SL50F484I4LG vs EP3SL50F484I4L Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SL50F484I4LG sa pamamagitan ng Intel at EP3SL50F484I4L sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP3SL50F484I4LG - Stratix III L FPGA, 47.5K LE, 484-FCBGA | Altera (Intel)
EP3SL50F484I4LG NrndPagsanggunian na paghahambing
| Parametro | EP3SL50F484I4LG | EP3SL50F484I4L |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Family | Stratix III L | Stratix III |
| Series | EP3SL50 | Stratix III L (Low Power) |
| Logic Elements | 47,500 | — |
| Embedded Memory | 2,184,192 bits (273 KB) | — |
| User I/Os | 296 | — |
| Packhaging | 484-Ball FCBGA (FBGA) | 484-ball FBGA (FCBGA) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | -40C to +100C (Industrial) | 0 °C to 85 °C (commercial, per DigiKey listing) |
| Speed Grade | I4 (fast) | 4 |
| Volte ng Pagbibigay | 0.85 V / 1.1 V / 1.2 V / 2.5 V / 3.3 V (multi-rail) | 0.9 V core (family-typical) |
| Process Node | 40 nm | — |
| Tindminan RoHS | Compliant | — |
| Lead-Free | Yes | — |
| Total I/O Banks | [DATA_NEEDED: I/O bank count] | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | Family supports up to 384 18x18 multipliers (family-level) |
| Transceivers | [DATA_NEEDED: transceiver channel count] | Family supports up to 4 transceivers per family datasheet |
| Configuration Memory | SRAM-based | — |
| Configuration Interface | JTAG / Passive Serial / Fast Passive Parallel | — |
| Logic Elements (LE) | — | 47,500 |
| Embedded Memory Bits | — | 2,184,192 bits (~273 KB) |
| User I/O Pins | — | 296 |
| Process Technology | — | 65 nm low-power CMOS |
| Lead-Free / RoHS | — | Yes (RoHS compliant) |
| Configuration Modes | — | Passive Serial, Fast Passive Parallel, JTAG |