EP3SL50F484I4LG vs EP3SL50F484I4L 比較
詳細並排比較 EP3SL50F484I4LG 由 Intel 與 EP3SL50F484I4L 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EP3SL50F484I4LG - Stratix III L FPGA, 47.5K LE, 484-FCBGA | Altera (Intel)
EP3SL50F484I4LG Nrnd規格比較
| 參數 | EP3SL50F484I4LG | EP3SL50F484I4L |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Family | Stratix III L | Stratix III |
| Series | EP3SL50 | Stratix III L (Low Power) |
| Logic Elements | 47,500 | — |
| Embedded Memory | 2,184,192 bits (273 KB) | — |
| User I/Os | 296 | — |
| 封裝 | 484-Ball FCBGA (FBGA) | 484-ball FBGA (FCBGA) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | -40C to +100C (Industrial) | 0 °C to 85 °C (commercial, per DigiKey listing) |
| Speed Grade | I4 (fast) | 4 |
| 供應電壓 | 0.85 V / 1.1 V / 1.2 V / 2.5 V / 3.3 V (multi-rail) | 0.9 V core (family-typical) |
| Process Node | 40 nm | — |
| RoHS 狀態 | Compliant | — |
| Lead-Free | Yes | — |
| Total I/O Banks | [DATA_NEEDED: I/O bank count] | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | Family supports up to 384 18x18 multipliers (family-level) |
| Transceivers | [DATA_NEEDED: transceiver channel count] | Family supports up to 4 transceivers per family datasheet |
| Configuration Memory | SRAM-based | — |
| Configuration Interface | JTAG / Passive Serial / Fast Passive Parallel | — |
| Logic Elements (LE) | — | 47,500 |
| Embedded Memory Bits | — | 2,184,192 bits (~273 KB) |
| User I/O Pins | — | 296 |
| Process Technology | — | 65 nm low-power CMOS |
| Lead-Free / RoHS | — | Yes (RoHS compliant) |
| Configuration Modes | — | Passive Serial, Fast Passive Parallel, JTAG |