EP4CGX110DF31C8 vs EP4CGX110DF31I7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP4CGX110DF31C8 sa pamamagitan ng Intel at EP4CGX110DF31I7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP4CGX110DF31C8 | EP4CGX110DF31I7 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | Cyclone IV GX | Cyclone IV GX |
| Family | Cyclone IV GX (EP4CGX110) | — |
| Device Type | FPGA - Field Programmable Gate Array | — |
| Logic Elements | 109,424 | — |
| Embedded Memory | 5,621,760 bits (M9K blocks) | — |
| Number of Logic Array Blocks (LABs) | [DATA_NEEDED: exact LAB count] | Not specified in provided data [DATA_NEEDED: LAB count] |
| Number of I/O | 475 | 475 user I/O |
| Number of Transceivers | Up to 8 (3.125 Gbps) | — |
| Embedded Multipliers (18x18) | 486 | — |
| Number of PLLs | [DATA_NEEDED: PLL count] | — |
| Supply Voltage (Core) | 1.2 V | — |
| Process Technology | 60 nm | — |
| Operating Temperature Grade | Commercial (0 C to 85 C), C-suffix | — |
| Packhaging | 896-FBGA, 31 mm x 31 mm, 1 mm pitch | 896-BGA (FBGA-896), 31 mm |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| PCIe Hard IP | Yes (integrated PCIe Gen1) | — |
| Configuration | JTAG, Active Serial (AS), Passive Serial (PS), Fast Passive Parallel (FPP) | — |
| Design Software | Quartus Prime (Qsys / Platform Designer) | — |
| Tindminan RoHS | Compliant (per datasheet) | Compliant |
| Device Logic Elements | — | 109,424 |
| Total Memory Bits | — | 5,621,760 |
| Multipliers (18x18) | — | 432 |
| PLLs | — | 4 |
| Transceivers | — | 8 (up to 3.125 Gbps) |
| M9K Memory Blocks | — | 270 |
| Ball Pitch | — | 0.8 mm |
| Speed Grade | — | -7 |
| Temperature Grade | — | Industrial (-40C to +100C Tj) |
| Core Voltage | — | 1.2 V typical |
| Configuration Method | — | SRAM (EPCS or JTAG) |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) [DATA_NEEDED: floor life days] |