EP610DC-20 vs EP610DC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610DC-20 sa pamamagitan ng Intel at EP610DC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610DC-20 | EP610DC-15 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | CMOS UV-Erasable Programmable Logic Device (EPLD) | — |
| Family | Classic EP610 | — |
| Logic Macrocells | 16 | — |
| Dedicated Inputs | 4 | 20 |
| I/O Pins | 16 (bidirectional) | — |
| Total Usable Pins | 20 | — |
| Product Terms (p-terms) | 160 | — |
| Propagation Delay (tPD) | 22 ns | 15 ns (speed grade -15) |
| Maximum Toggle Frequency (fMAX) | 55.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V |
| Temperature na Operasyon | 0 °C to 70 °C (commercial) | 0C to 70C (commercial) |
| Packhaging | 24-pin Ceramic DIP (CDIP-24) with UV window | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Programming Method | UV erasure + parallel programmer | JEDEC fuse map, UV erasure |
| Process Technology | CMOS, UV-erasable floating gate | — |
| Uri ng Pagpapasok | Through-hole | Through-Hole |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Product Family | — | Classic EPLD (EP610) |
| Architecture | — | UV-erasable CMOS PAL-type |
| Macrocells | — | 16 |
| Logic Expanders | — | 4 |
| Bidirectional I/O Pins | — | 16 |
| Total Product Terms | — | 160 |
| Maximum Internal Clock Frequency | — | 71.4 MHz |
| Technology | — | CMOS |