EP610DC-20 vs EP610DC-15 比較
詳細並排比較 EP610DC-20 由 Intel 與 EP610DC-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610DC-20 | EP610DC-15 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | CMOS UV-Erasable Programmable Logic Device (EPLD) | — |
| Family | Classic EP610 | — |
| Logic Macrocells | 16 | — |
| Dedicated Inputs | 4 | 20 |
| I/O Pins | 16 (bidirectional) | — |
| Total Usable Pins | 20 | — |
| Product Terms (p-terms) | 160 | — |
| Propagation Delay (tPD) | 22 ns | 15 ns (speed grade -15) |
| Maximum Toggle Frequency (fMAX) | 55.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V |
| 工作溫度 | 0 °C to 70 °C (commercial) | 0C to 70C (commercial) |
| 封裝 | 24-pin Ceramic DIP (CDIP-24) with UV window | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Programming Method | UV erasure + parallel programmer | JEDEC fuse map, UV erasure |
| Process Technology | CMOS, UV-erasable floating gate | — |
| 安裝類型 | Through-hole | Through-Hole |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Product Family | — | Classic EPLD (EP610) |
| Architecture | — | UV-erasable CMOS PAL-type |
| Macrocells | — | 16 |
| Logic Expanders | — | 4 |
| Bidirectional I/O Pins | — | 16 |
| Total Product Terms | — | 160 |
| Maximum Internal Clock Frequency | — | 71.4 MHz |
| Technology | — | CMOS |