EP610DC-30 vs EP610DC-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610DC-30 sa pamamagitan ng Altera at EP610DC-20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610DC-30 | EP610DC-20 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | CMOS UV-Erasable Programmable Logic Device (EPLD) |
| Family | EP610 (Classic Device Family) | Classic EP610 |
| Macrocells | 16 | — |
| Logic Expanders | 4 (4 product terms per macrocell) | — |
| Usable Gates | 300 | — |
| Maximum Pipelined Clock Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 30 ns | 22 ns |
| Dedicated Inputs | 16 | 4 |
| I/O Pins | 16 (with output enable) | 16 (bidirectional) |
| Packhaging | 24-pin CERDIP (windowed) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Uri ng Pagpapasok | Through-Hole | Through-hole |
| Speed Grade | -30 (30 ns tPD) | — |
| Technology | CMOS EPROM | — |
| Programmability | UV-erasable, windowed EPROM | — |
| Security Bit | Yes (protects design after programming) | — |
| Output Modes | Registered and Combinatorial | — |
| Temperature na Operasyon | Commercial (0C to +70C) | 0 °C to 70 °C (commercial) |
| Logic Macrocells | — | 16 |
| Total Usable Pins | — | 20 |
| Product Terms (p-terms) | — | 160 |
| Maximum Toggle Frequency (fMAX) | — | 55.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Programming Method | — | UV erasure + parallel programmer |
| Process Technology | — | CMOS, UV-erasable floating gate |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |