EP610DC-30 vs EP610ILC-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610DC-30 sa pamamagitan ng Altera at EP610ILC-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610DC-30 | EP610ILC-10 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | UV-Erasable / OTP PLD |
| Family | EP610 (Classic Device Family) | — |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 (4 product terms per macrocell) | — |
| Usable Gates | 300 | 300 |
| Maximum Pipelined Clock Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 30 ns | — |
| Dedicated Inputs | 16 | 4 |
| I/O Pins | 16 (with output enable) | 16 |
| Packhaging | 24-pin CERDIP (windowed) | PLCC-28 (plastic J-lead chip carrier) |
| Uri ng Pagpapasok | Through-Hole | Surface Mount (PLCC socket or solder) |
| Speed Grade | -30 (30 ns tPD) | — |
| Technology | CMOS EPROM | — |
| Programmability | UV-erasable, windowed EPROM | — |
| Security Bit | Yes (protects design after programming) | — |
| Output Modes | Registered and Combinatorial | — |
| Temperature na Operasyon | Commercial (0C to +70C) | [DATA_NEEDED: operating temperature range] |
| Device Family | — | Classic EPLD |
| Architecture | — | PAL-type with macrocells |
| Product Terms | — | 160 |
| Volte ng Pagbibigay | — | 5 V (single supply) |
| Pin-to-Pin Delay (tPD) | — | 10 ns (grade -10) |
| Counter Frequency (fCNT) | — | 100 MHz |
| Logic Family Compatibility | — | TTL (5 V CMOS/TTL-compatible I/O) |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS compliance] |