EP610DC35 vs EP610DC15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610DC35 sa pamamagitan ng Altera at EP610DC15 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610DC35 | EP610DC15 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | Classic EPLD | EP610 Classic EPLD |
| Logic Elements | 16 macrocells | — |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 35 ns | 15 ns |
| Maximum Frequency | 28.6 MHz | — |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Volte ng Pagbibigay | 5 V | — |
| Packhaging | 24-pin CDIP (Ceramic DIP) with quartz erase window | 24-pin CDIP (Ceramic DIP, windowed) |
| Uri ng Pagpapasok | Through-Hole | Through-Hole |
| Bilang ng Pin | 24 | — |
| Technology | UV-erasable CMOS EPROM | CMOS |
| Programming Method | Altera legacy programmer (PLDLMax or compatible) | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | 0C to +70C |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| I/O Pins | [DATA_NEEDED: number of user I/O pins] | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 16 |
| Architecture | — | PAL-type |
| Maximum Clock Frequency (fMAX) | — | 71.4 MHz |
| Total Inputs | — | 20 |
| I/O Lines | — | 16 |
| Product Terms | — | 160 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Reprogrammability | — | Yes (UV erasable via windowed package) |