EP610DC35 vs EP610DC15 比較
詳細並排比較 EP610DC35 由 Altera 與 EP610DC15 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610DC35 | EP610DC15 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | Classic EPLD | EP610 Classic EPLD |
| Logic Elements | 16 macrocells | — |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 35 ns | 15 ns |
| Maximum Frequency | 28.6 MHz | — |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| 供應電壓 | 5 V | — |
| 封裝 | 24-pin CDIP (Ceramic DIP) with quartz erase window | 24-pin CDIP (Ceramic DIP, windowed) |
| 安裝類型 | Through-Hole | Through-Hole |
| 腳位數 | 24 | — |
| Technology | UV-erasable CMOS EPROM | CMOS |
| Programming Method | Altera legacy programmer (PLDLMax or compatible) | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | 0C to +70C |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| I/O Pins | [DATA_NEEDED: number of user I/O pins] | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 16 |
| Architecture | — | PAL-type |
| Maximum Clock Frequency (fMAX) | — | 71.4 MHz |
| Total Inputs | — | 20 |
| I/O Lines | — | 16 |
| Product Terms | — | 160 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Reprogrammability | — | Yes (UV erasable via windowed package) |