EP610DM-35 vs EP610DI-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610DM-35 sa pamamagitan ng Altera at EP610DI-25 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610DM-35 | EP610DI-25 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Manufacturer | Altera (Rochester Electronics authorized stock) | — |
| Part Family | Classic EPLD | Classic EPLD |
| Logic Family | PAL-type EPLD, CMOS, UV-erasable | — |
| Number of Macrocells | 16 | — |
| Number of Gates | 300 | — |
| Propagation Delay (tPD) | 35 ns | 25 ns |
| Pipelined Data Rate (fMAX) | 100 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V nominal |
| Packhaging | 24-pin CDIP (CERDIP) with UV window | — |
| Temperature Grade (M) | Military -55°C to +125°C | — |
| I/O Pins | 24 dedicated I/O (input + bidirectional) | 16 (bidirectional) |
| Programmability | UV-erasable, reprogrammable | — |
| Hanay ng Temperature na Operasyon | -55°C to +125°C | — |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Tindminan RoHS | Non-compliant (contains lead, hermetic CERDIP) | — |
| Macrocells | — | 16 |
| Maximum Pipelined Clock Frequency | — | 100 MHz (max fCNT, per family datasheet) |
| Dedicated Inputs | — | 4 |
| Total User I/O | — | 20 |
| Technology | — | CMOS EPROM (UV-erasable) |
| Package Type | — | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 |
| Bilang ng Pin | — | 24 |
| Uri ng Pagpapasok | — | Through-Hole (DIP) |
| Temperature na Operasyon | — | Industrial (per "I" suffix) |
| Speed Grade Suffix | — | 25 = 25 ns |
| Compliance | — | RoHS status unknown (legacy 1990s part) |