EP610DM-35 vs EP610DI-25 比較
詳細並排比較 EP610DM-35 由 Altera 與 EP610DI-25 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610DM-35 | EP610DI-25 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Manufacturer | Altera (Rochester Electronics authorized stock) | — |
| Part Family | Classic EPLD | Classic EPLD |
| Logic Family | PAL-type EPLD, CMOS, UV-erasable | — |
| Number of Macrocells | 16 | — |
| Number of Gates | 300 | — |
| Propagation Delay (tPD) | 35 ns | 25 ns |
| Pipelined Data Rate (fMAX) | 100 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V nominal |
| 封裝 | 24-pin CDIP (CERDIP) with UV window | — |
| Temperature Grade (M) | Military -55°C to +125°C | — |
| I/O Pins | 24 dedicated I/O (input + bidirectional) | 16 (bidirectional) |
| Programmability | UV-erasable, reprogrammable | — |
| 工作溫度範圍 | -55°C to +125°C | — |
| MSL 等級 | [DATA_NEEDED: MSL rating] | — |
| RoHS 狀態 | Non-compliant (contains lead, hermetic CERDIP) | — |
| Macrocells | — | 16 |
| Maximum Pipelined Clock Frequency | — | 100 MHz (max fCNT, per family datasheet) |
| Dedicated Inputs | — | 4 |
| Total User I/O | — | 20 |
| Technology | — | CMOS EPROM (UV-erasable) |
| Package Type | — | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 |
| 腳位數 | — | 24 |
| 安裝類型 | — | Through-Hole (DIP) |
| 工作溫度 | — | Industrial (per "I" suffix) |
| Speed Grade Suffix | — | 25 = 25 ns |
| Compliance | — | RoHS status unknown (legacy 1990s part) |